Japanese patent application no. 2000-109309, filed Apr. 11, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device including a memory cell section such as an SRAM (Static Random Access Memory).
An SRAM does not need refreshing. Therefore, the SRAM enables system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones. There has been a demand for miniaturization of portable devices on which the SRAM is mounted. To deal with this demand, the memory cell size of the SRAM must be reduced.
An objective of certain embodiments of the present invention is to provide a semiconductor device capable of reducing memory cell size.
A semiconductor device according to one embodiment of the present invention comprises a memory cell section and a semiconductor circuit section other than the memory cell section that are formed on the same semiconductor substrate, the memory cell section having a plurality of memory cells each of which includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:
each of the memory cells comprises a first gate electrode layer, a second gate electrode layer, a first drain-drain contact layer, a second drain-drain contact layer, a first drain-gate contact layer, and a second drain-gate contact layer;
the first gate electrode layer comprises a gate electrode of the first driver transistor and a gate electrode of the first load transistor;
the second gate electrode layer comprises a gate electrode of the second driver transistor and a gate electrode of the second load transistor;
the first drain-drain contact layer and the second drain-drain contact layer are located above the first gate electrode layer and the second gate electrode layer;
the first gate electrode layer and the second gate electrode layer are located between the first drain-drain contact layer and the second drain-drain contact layer, as seen in a plan view of the memory cells;
the first drain-drain contact layer is used to connect a drain region of the first driver transistor to a drain region of the first load transistor;
the second drain-drain contact layer is used to connect a drain region of the second driver transistor to a drain region of the second load transistor;
the first drain-gate contact layer and the second drain-gate contact layer are located above the first drain-drain contact layer and the second drain-drain contact layer;
the first drain-gate contact layer is used to connect the first drain-drain contact layer to the second gate electrode layer;
the second drain-gate contact layer is used to connect the second drain-drain contact layer to the first gate electrode layer; and
the semiconductor circuit section has no wiring layer at the same level as the first drain-drain contact layer and the second drain-drain contact layer.
The semiconductor device of another embodiment of the present invention includes the gate electrode layers which become gates of inverters, the drain-drain contact layers for connecting drains of the inverters, and the drain-gate contact layers for connecting the gate of one inverter to the drain of the other inverter. In this semiconductor device, a flip-flop is formed using three layers (gate electrode layer, drain-drain contact layer, and drain-gate contact layer). Therefore, the pattern of each layer can be simplified (linear pattern, for example) in comparison with the case of forming a flip-flop using two layers. According to this embodiment of the present invention, since the pattern of each layer can be simplified, a miniaturized semiconductor device with a memory cell size of 4.5 xcexcm2 or less can be fabricated.
The first gate electrode layer and the second gate electrode layer are located between the first drain-drain contact layer and the second drain-drain contact layer in a plan view. Therefore, a source contact layer of the driver transistors can be disposed at the center of the memory cell. Moreover, a wiring layer formed in the same layer as the drain-drain contact layer to which the source contact layer is connected can be disposed at the center of the memory cell. Therefore, the degree of freedom relating to formation of the first and second drain-gate contact layers can be increased. This also ensures reduction of the memory cell size. The source contact layer is a conductive layer used to connect the source region of the driver transistor to the wiring layer.
Another embodiment of the present invention may increase the speed of the semiconductor circuit section with miniaturized memory cells embedded. Specifically, another embodiment of the present invention may use a refractory metal nitride layer as the first and second drain-drain contact layers, as described later. A refractory metal nitride layer exhibits relatively high electric resistance. Therefore, when a refractory metal nitride layer is used as the wiring layer in the semiconductor circuit section, the speed of the semiconductor circuit section cannot be increased. Since the semiconductor circuit section does not have a wiring layer at the same level as the first and second drain-drain contact layers, the speed of the semiconductor circuit section can be increased.
A thickness of the first drain-drain contact layer and the second drain-drain contact layer may be 100 nm to 170 nm. This is because the first and second drain-drain contact layers with a thickness of 100 nm or more exhibit suitable electric resistance values. When the thickness of the first and second drain-drain contact layers is 170 nm or less, the thickness of an interlayer dielectric located on the first and second drain-drain contact layers does not become too great. This ensures that the aspect ratio of hole section (through-hole, for example) formed in the interlayer dielectric is decreased (5 or less, for example). The thickness of the first and second drain-drain contact layers may be adjusted to 170 nm or less by allowing a refractory metal nitride layer such as titanium nitride to be included in the first and second drain-drain contact layers.
The semiconductor device of another embodiment of the present invention may further comprise a field effect transistor, a first interlayer dielectric, a second interlayer dielectric, a wiring layer, and a contact-conductive section, wherein:
the field effect transistor may be located in the semiconductor circuit section;
the first interlayer dielectric may be located in the memory cell section so as to cover the first gate electrode layer and the second gate electrode layer;
the first interlayer dielectric may be located in the semiconductor circuit section so as to cover a gate electrode of the field effect transistor;
the second interlayer dielectric may be formed in the memory cell section so as to cover the first drain-drain contact layer and the second drain-drain contact layer;
the second interlayer dielectric may be located on the first interlayer dielectric in the semiconductor circuit section;
the wiring layer may be located on the second interlayer dielectric in the semiconductor circuit section;
the wiring layer may be located at the same level as the first drain-gate contact layer and the second drain-gate contact layer;
the contact-conductive section may be located in a hole section formed through the first interlayer dielectric and the second interlayer dielectric in the semiconductor circuit section; and
the contact-conductive section may be used to connect the wiring layer to at least one of a source/drain of the field effect transistor and a gate electrode of the field effect transistor.
The wiring layer may be connected to the source/drain and the gate electrode of the field effect transistor using the contact-conductive section without forming a contact pad layer between the first interlayer dielectric and the second interlayer dielectric. Therefore, the fabrication process of the semiconductor circuit section can be simplified.
The aspect ratio of the hole section may be 5 or less. The hole section with an aspect ratio of 5 or less can be easily filled with the contact-conductive section.
The semiconductor circuit section may comprise a logic circuit section. This is because higher speed is required for the logic circuit section. For example, the logic circuit section includes a gate array, standard cell, and system LSI.
The first gate electrode layer, the second gate electrode layer, the first drain-drain contact layer, and the second drain-drain contact layer respectively may have a linear pattern and may be disposed in parallel one another. Since the pattern of each layer is simple, a semiconductor device with a minute memory cell size can be fabricated.
With the semiconductor device of another embodiment of the present invention,
the first driver transistor and the second driver transistor may be n-type;
the first load transistor and the second load transistor may be p-type;
the first transfer transistor and the second transfer transistor may be n-type;
the memory cell section may comprise a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;
the first gate electrode layer, the second gate electrode layer, and a sub-word line may be located in the first conductive layer;
the first drain-drain contact layer, the second drain-drain contact layer, a power supply line, a first contact pad layer, a second contact pad layer, and a third contact pad layer may be located in the second conductive layer;
the first drain-gate contact layer, the second drain-gate contact layer, a main-word line, a fourth contact pad layer, a fifth contact pad layer, and a sixth contact pad layer may be located in the third conductive layer;
a first bit line, a second bit line, and a ground line may be located in the fourth conductive layer;
the sub-word line may extend in a first direction;
the power supply line may be connected to a source region of the first load transistor and the second load transistor;
the first contact pad layer may be used to connect the first bit line to a source/drain region of the first transfer transistor;
the second contact pad layer may be used to connect the second bit line to a source/drain region of the second transfer transistor;
the third contact pad layer may be used to connect a source region of the first driver transistor and the second driver transistor to the ground line;
the main-word line may extend in the first direction;
the fourth contact pad layer may be used to connect the first bit line to a source/drain region of the first transfer transistor;
the fifth contact pad layer may be used to connect the second bit line to a source/drain region of the second transfer transistor;
the sixth contact pad layer may be used to connect a source region of the first driver transistor and the second driver transistor to the ground line; and
the first bit line and the second bit line may extend in a second direction which intersects the first direction at right angles.
According to another embodiment of the present invention, various performances (miniaturization, reliability, stability, and speed, for example) required for semiconductor devices can be increased while balancing these performances.